One-time programmable (OTP) and multiple-time programmable (MTP) memory devices are employed to meet various non-volatile memory requirements of many applications while offering low power operation, low cost, and excellent reliability while maintaining compatibility with existing complementary metal-oxide semiconductor (CMOS) processes without the need for extra masks. As a result, CMOS logic compatible MTP/OTP embedded memory provides a cost effective and simple process that is flexible among foundries. OTP and MTP memory devices also provide solutions that can be tailored to the specific application. For example, OTP memory devices may often be implemented with a small device footprint while MTP memory devices provide a high number of write/erase cycles from a single unit cell.
Known programmable cells include a select transistor coupled in series with a program transistor. A bitline is connected to a source region of the select transistor. When a normal supply voltage such as an I/O or core voltage is applied to the gates of the programmable cell, no current is sensed along the bitline. The equivalent circuit for the program transistor is a capacitor. Since there is no current that flows along the bitline, the cell is “0” by default. When a large programming voltage is applied along the gate of the program transistor, gate dielectric breakdown occurs and a resistive path is created. The equivalent circuit for the program transistor becomes a resistor. A normal supply voltage applied to the gates of the programmable cell after programming result in current flow along the bitline and a “1” is sensed. The program transistors can be programmed at any time. Once programmed, the program transistors of an OTP memory cell cannot be reverted back to a “0”. In contrast, the program transistors of a MTP memory cell can be reverted back to a “0”.
In the known programmable cell, there is a select transistor for each distinct program transistor. Stated differently, two adjacent programmable memory cells would have a total of four distinct transistors. Reducing the overall size of transistors and memory devices allows for, among other benefits, increased yield, reduced, heat, and lower operating voltage. However, simply reducing the distance between adjacent memory cells may yield undesirable results. For example, programming voltage used to program one cell (the target cell) can leak to a cell adjacent the target cell causing potential dielectric damage and poor cell performance.
Accordingly, it is desirable to provide integrated circuits including programmable memory devices that have a smaller device footprint along with reliable performance while maintaining effective isolation between the cells of the device. Further, it is desirable to provide methods of forming the integrated circuits that have the smaller device footprint within existing fabrication schemes without the need for added masking and patterning techniques. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.